The present invention relates to integrated circuit fabrication, and specifically to structures and methods for electrical testing and/or for process monitoring and/or parasitic extraction accuracy monitoring and/or building statistical interconnect models based on silicon measurements.
A critical part of semiconductor manufacturing and design is the testing of integrated circuits. Before the functionality tests at the end of processing, additional testing for process monitoring is also useful. Testing for process monitoring uses special test structures which are not part of the integrated circuit""s functionality. Process monitoring helps to detect problems that may cause reliability problems in the field, helps to optimize the process for maximum yield, and helps to catch any process deviations before too much work-in-process is wasted.
Typical electrical test structures for in-process testing are long series-connected chains of similar elements (to test for excessive resistance or open circuits). The test structure will also include two or more xe2x80x9cprobe pads,xe2x80x9d which are flat metal surface that electrical connection can be made to them in the test lab. These test structures are manufactured at the same time as the functional circuitry, using the same process steps, but are specially designed to test particular process parameters. (For example, to test for specific contact resistance a chain of thousands of series-connected contacts might be created.) A large variety of test structures are used by process engineers to test various process stages and device portions.
A xe2x80x9cwaferxe2x80x9d is a flat disk of semiconductor material on which integrated circuits are made by micro-fabrication techniques. After fabrication is complete, the wafer will be separated into rectangular xe2x80x9cdice,xe2x80x9d each of which is the electronics portion of one integrated circuit. The dice will be packaged to provide the end-product integrated circuits. Typically one wafer will provide dozens or hundreds of dice.
When the dice are separated, some of the wafer surface between them is wasted. This space is known as xe2x80x9cscribelines,xe2x80x9d since the dice were formerly separated by scribing and fracturing; now that diamond sawing has replaced scribing, these spaces are also known as xe2x80x9csaw streets.xe2x80x9d
Test structures are placed within the scribelines of the wafer (and in other places), typically once or more per photolithographic field. Typical scribeline test structures are individually connected to corresponding probe pads, also located in the scribelines. Since the area within the scribelines is densely occupied, the size and number of probe pads is critical. However, probe pad size has not scaled as fast as other process steps, and the space available within the scribelines is very limited. Placing multiple test structures and probe pads for those test structures within this limited area becomes difficult in many processes, and limits the testing of the wafer fabrication process. Limits to the testing capability lead to less reliable integrated circuits.
Scribeline widths, as of 2002 are typically less than a tenth of a millimeter. Probe pads are typically made just small enough to fit within the scribeline. These dimensions can be expected to change over time, in dependence on wafer fabrication and separation technologies; but the key point is that each probe pad occupies a very significant fraction of the limited available scribeline area.
Since each probe pad nearly fills the width of a scribeline, the layout of test structures in the scribelines is often somewhat one-dimensional. That is, a test structure in the scribelines can be allowed to take up nearly the entire width of the scribeline, and extended along the scribeline as far as necessary.
Some space in the corners of the dice themselves is typically also allocated for test patterns, but again the available area is limited. Typically several to several tens of test structures can fit into each corner of a die.
Some space for test structures is also available along the edge of the wafer, where the grid of square or rectangular dice meets the unusable width of the rounded edge. While these spaces are relatively large, they are far from the important central areas of the wafer. Thus test structures in the edge-of-wafer corners cannot provide sufficiently close monitoring of process variation, including spatial variation across the wafer.
One basic tool for process monitoring is the use of pilot wafers. Some manufacturers will start several pilot or dummy wafers for each wafer that will produce actual chips. While some use of pilot wafers will always be common (e.g. at the head of each lot), every pilot wafer start takes the place of a wafer full of salable chips. Thus to the extent that sufficient process monitoring can be done using on-chip test and monitoring structures, this is greatly preferable to use of pilot wafers. Dummy wafers, on the other hand, are used to ensure that equipment has stabilized, e.g. when a bulk furnace is being ramped up or when a wet processing station has been refilled. Use of such dummy wafers is not motivated by process monitoring needs, and hence would not appear to be subject to trade-off against on-wafer test structures.
U.S. Pat. publication 20020047724, entitled xe2x80x9cMulti-state test structures and methods,xe2x80x9d describes a selection capability that radically increases the number of test structures per probe pad. By adding a test selector to the test structure, multiple test structures are multiplexed to one (or more) probe pads. Selection of which test structure is to be accessed from a given probe pad is preferably performed entirely by control of the voltage applied across the probe pads. In one class of embodiments, the applied voltage directly determines which test structure will be accessed. In another class of embodiments, modulation of the applied voltage controls sequential logic that selects one of multiple test structures for access.
In the past, circuit delay has been due mostly to transistors. Today, the dominant source of delay in circuits such as ASICs and microprocessor is metal interconnect. FIG. 1 is a schematic diagram of a prior art charge-based capacitance measurement (CBCM) structure for measuring parasitic capacitance. A paper entitled xe2x80x9cAn On-Chip, Attofarad Interconnect Charge-Based Capacitance Measurement (CBCM) Technique,xe2x80x9d Proc. of IEDM 1996, pp. 69-72, discloses an improved test structure for performing CBCM that included an on-chip signal generator and an entirely new measurement scheme as well. The resolution limit of the methodology is estimated to be 0.01 fF, hence making it more than adequate for characterizing parasitic interconnect capacitances.
In this paper, a test structure is disclosed that comprises a pair of NMOS and PMOS transistors connected in a xe2x80x9cpseudoxe2x80x9d inverter configuration two form two inverters 100, 101. Inverter 100 is a reference inverter used to achieve the highest resolution. Inverter 100 is identical to inverter 101 in every manner except that it does not include the target capacitance to be characterized. Inverter 101 is connected to the target device that is to be measured. For example, in FIG. 1 the target device consists of level 2 metal line 111 and level 1 metal line 112 that form an intersection at 110. This structure is used to measure the resulting interconnect capacitance between the two lines. The reference inverter is connected to metal 1 line 113 that is the same configuration as line 112, but does not contain the metal 1 to metal 2 overlap capacitance that is to be measured.
FIG. 2 is a timing diagram illustrating non-overlapping clock signals used by the prior art CBCM structure of FIG. 1. The V1, and V2 signals of FIG. 1 consist of two non-overlapping signals shown in FIG. 2. These signals can be either generated off-chip or on chip. The purpose of these non-overlapping waveforms is to ensure that only one of the two transistors in each test structure inverter is conducting current at any given time. Thus, short-circuit current from Vdd to ground is eliminated. When the PMOS transistor turns on, it will draw charge from Vdd to charge up the target interconnect capacitance.
This amount of charge will then be subsequently discharged through the NMOS transistor into ground. An ammeter can be placed at the source of the PMOSFET (or, alternatively at the source of the NMOSFET) to measure this charging current. The actual waveform of this charging current is of no consequence; only its DC or average current value needs to be measured. DC current can be easily obtained from any modern current meter. The difference between the two DC current values in FIG. 1 is used to extract the target interconnect capacitance as shown by equations 1 and 2 below.
Ixe2x80x94Iref=Inetxe2x80x83xe2x80x83(1)
                    C        =                              I            net                                              V              dd                        ·            f                                              (        2        )            
CBCM can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances; including metal to substrate, interwire, and interlayer capacitances, as discussed in a paper entitled xe2x80x9cInvestigation of Interconnect Capacitance using Charge-Based Capacitance Measurement (CBCM) Technique and 3-Dimensional Simulationxe2x80x9d, IEEE JSSC, pp. 449-453, March 1998. However, this paper teaches that several test structures must be utilized to decouple vertical and horizontal capacitive components from the total capacitance.
Therefore, there is still a need in the art for a way to increase the efficiency of space usage for test structures within the scribelines of an integrated circuit process.
An apparatus is provided for testing a partially fabricated wafer using a test structure located within the scribe lines of the wafer. The test structure includes a first structure overlying a substrate and coupled to a first probe pad, such that the first structure has a first parasitic capacitance relative to the substrate. A second structure is located in proximity to the first structure, such that the first structure has a second parasitic capacitance relative to the second structure. A bias circuit is coupled to the second structure and has an input coupled to a second probe pad. The bias circuit is operable to bias the second structure in response to a select signal impressed on the second probe pad. A test signal impressed on the first probe pad is operable to provide a measure of the first parasitic capacitance when the select signal has a first value; and the test signal is operable to provide a measure of the second parasitic capacitance when the select signal has a second value.
A method for testing a partially fabricated wafer is provided that comprises the following steps:
a) providing a device under test (DUT) overlying a substrate of the wafer;
b) biasing a second structure located in proximity to the DUT to have a first electrical state such that a first equivalent test structure is formed;
c) determining a first parasitic parameter associated with the first equivalent test structure by applying a signal to the DUT while the second structure is in the first electrical state and measuring a response that is indicative of the first parameter;
d) biasing the second structure to have a second electrical state such that a second equivalent test structure is formed; and
e) determining a second parasitic parameter associated with the second equivalent test structure by applying a signal to the DUT while the second structure is in the second electrical state and measuring a response that is indicative of the second parameter.
Advantages of the disclosed methods and structures, in various embodiments, can include one or more of the following: more test structures can be used on a given wafer; test structures can be made larger; quicker correction of process deviations; increased efficiency of use of wafer area; increased efficiency of use of scribeline area; fewer probe pads are needed; increased yield; and increased capability for xe2x80x9cearly warningxe2x80x9d testing increases reliability of the integrated circuits.